1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2009-283947, filed Dec. 15, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
As shrinkage of semiconductor devices has been progressed, the dimension (or gate length) of a gate electrode of a metal-oxide-semiconductor (MOS)-type transistor has been reduced, and the influence of a short channel effect on electrical characteristics has become more serious.
For suppressing the short channel effect of the MOS transistor, a silicon layer is formed in source and drain regions using an epitaxial growth process, which is disclosed in Japanese Patent Application Laid-Open No. 2007-134732.
For suppressing the short channel effect of the MOS transistor, a pocket layer of an opposite conductivity type to impurities for forming source and drain regions is formed, which is disclosed in Japanese Patent Application Laid-Open No. 6-196492.